In a semiconductor device disclosed in Japanese Unexamined Patent Application Publication No 2001-325795 a memory cell array is composed of a plurality of cores, in which a memory cell range as a unit of erasing data is a block, and a set of one to a plurality of blocks is one core and a plurality of cores, are arranged. An arbitrary number of cores are selected by core selecting means, data is written into the selected memory cell in the core, and data is erased from the selected block in the core. During this period, data is read out in the memory cell in the core not selected. An arbitrary core is selected, and data is written or erased, and at the same time data can be, read out in other arbitrary core. The range of simultaneous operation is not limited, and a flash memory of high degree of freedom is realized.
In this case, an address signal is given from outside by an address input circuit in the interface circuit, and supplied into an address buffer circuit. From the address buffer circuit, depending on the operation mode, the address is supplied to the address bus line for reading address, or address bus line for writing or erasing, and is selectively transferred to a decoding circuit of each decoding circuit of each core.
Japanese Unexamined Patent Application Publication No, 2001-325795 enables to set the bank size, supposing the range of an arbitrarily determined core to be one bank, when executing simultaneously a data writing or an erasing operation and a data reading operation. The data quantity demanded from the system varies in each access operation, and the memory cell region depending on the demanded data quantity can be specified as the object of access.
In Japanese Unexamined Patent Application Publication No, 2001-325795, however, regardless of difference in the access operation, such as data writing, erasing, and data reading, the access object of each access operation is applied to all memory cell arrays. On every occasion of the access operation, all address signals must be entered from outside. On the other hand, in the access operation accompanied by input and output of data such as the reading operation and the writing operation, the data quantity demanded in a series of access operation may be estimated within a range of specified quantity, and the memory cell region of the object of access can be stored in the specified region. However, in Japanese Unexamined Patent Application Publication No 2001-325795, when accessing the region of the same memory cell, although the higher address signal for specifying the memory cell region is unchanged, the signal is entered from outside on every occasion of access, and decoding process or the like is executed. Unnecessary input process of address signal must be done on every occasion of the access operation, and the input process of address signal is merely frequent.
In particular, as the storage device is increased in capacity, even a memory cell region forming part of the memory cell array may be equivalent to a memory capacity capable of storing sufficiently the data quantity demanded by the system, in such a case, it is a useless deed to enter constant higher address signal on every occasion of the access operation. By this circuit operation. By this circuit operation, limitations may occur in shortening of processing time and saving of current consumption or the like.
Further, due to increase in capacity of storage device, the address space for composing the memory cell array become wider, and the address signal is composed of multiple bits, and the address decoder in the storage device consists of multiple inputs and multiple logical stages. The address signal is decoded by the address decoder, and the memory cell as an object of access in the memory cell array is determined. If the setting time by the address decoder is delayed because of multiple inputs and multiple logical stages, problems occur that determination of the memory cell is delayed, and the memory cell access is retarded. Consequently, in response to the increase in the number of input terminals of the address signal in storage device and increase in control quantity by the memory controller, it is required to establish an efficient input interface technology of the address signal, and the high speed operation of the address decoder consisting of multiple inputs and multiple logical stages.